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  <br>
  <h1 id="tracecpu"><strong>TraceCPU</strong></h1>
<p>Table of Contents</p>

<ol>
  <li>
    <p><a href="##Overveiw">Overview</a></p>
  </li>
  <li><a href="##Elastic-Trace-Generation">Elastic Trace Generation</a>
    <ol>
      <li><a href="##Scripts-and-options">Scripts and options</a></li>
      <li><a href="###Trace-file-formats">Trace file format</a></li>
    </ol>
  </li>
  <li><a href="#replay-with-trace-cpu">Replay with Trace CPU</a>
    <ol>
      <li><a href="##Scripts-and-options">Scripts and options</a></li>
    </ol>
  </li>
</ol>

<h2 id="overview"><strong>Overview</strong></h2>
<p>The Trace CPU model plays back elastic traces, which are dependency and timing annotated traces generated by the Elastic Trace Probe attached to the O3 CPU model. The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy, interconnects and main memory) performance exploration in a fast and reasonably accurate way instead of using the detailed but slow O3 CPU model. The traces have been developed for single-threaded benchmarks simulating in both SE and FS mode. They have been correlated for 15 memory-sensitive SPEC 2006 benchmarks and a handful of HPC proxy apps by interfacing the Trace CPU with classic memory system and varying cache design parameters and DRAM memory type. In general, elastic traces can be ported to other simulation environments.</p>

<p><strong>Publication</strong>:</p>

<p><a href="https://ieeexplore.ieee.org/document/7818336">Exploring System Performance using Elastic Traces: Fast, Accurate and Portable”</a> Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung and Norbert Wehn SAMOS 2016</p>

<p><strong>Trace generation and replay methodology</strong></p>

<p><img src="/assets/img/Etrace_methodology.jpg" alt="Methodology block diagram showing elastic trace generation using O3 CPU and replay using Trace CPU
" /></p>

<h2 id="elastic-trace-generation"><strong>Elastic Trace Generation</strong></h2>
<p>The Elastic Trace Probe Listener listens to Probe Points inserted in O3 CPU pipeline stages. It monitors each instruction and creates a dependency graph by recording data Read-After-Write dependencies and order dependencies between loads and stores. It writes the instruction fetch request trace and the elastic data memory request trace as two separate files as shown below.</p>

<p><img src="/assets/img/Etraces_output.jpg" alt="Elastic trace file generation" /></p>

<h3 id="trace-file-formats"><strong>Trace file formats</strong></h3>

<p>The elastic data memory trace and fetch request trace are both encoded using google protobuf.</p>

<h5 id="elastic-trace-fields-in-protobuf-format"><strong>Elastic Trace fields in protobuf format</strong></h5>

<table>
  <thead>
    <tr>
      <th>Fields</th>
      <th>Discritption</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td>required uint64 seq_num  </td>
      <td>Instruction number used as an id for tracking dependencies</td>
    </tr>
    <tr>
      <td>required RecordType type  </td>
      <td>RecordType enum has values: INVALID, LOAD, STORE, COMP</td>
    </tr>
    <tr>
      <td>optional uint64 p_addr  </td>
      <td>Physical memory address if instruction is a load/store</td>
    </tr>
    <tr>
      <td>optional uint32 size  </td>
      <td>Size in bytes of data if instruction is a load/store</td>
    </tr>
    <tr>
      <td>optional uint32 flags  </td>
      <td>Flags or attributes of the access, ex. Uncacheable</td>
    </tr>
    <tr>
      <td>required uint64 rob_dep  </td>
      <td>Past instruction number on which there is order (ROB) dependency</td>
    </tr>
    <tr>
      <td>required uint64 comp_delay  </td>
      <td>Execution delay between the completion of the last dependency and the execution of the instruction  </td>
    </tr>
    <tr>
      <td>repeated uint64 reg_dep  </td>
      <td>Past instruction number on which there is RAW data dependency</td>
    </tr>
    <tr>
      <td>optional uint32 weight  </td>
      <td>To account for committed instructions that were filtered out</td>
    </tr>
    <tr>
      <td>optional uint64 pc  </td>
      <td>Instruction address, i.e. the program counter</td>
    </tr>
    <tr>
      <td>optional uint64 v_addr  </td>
      <td>Virtual memory address if instruction is a load/store</td>
    </tr>
    <tr>
      <td>optional uint32 asid  </td>
      <td>Address Space ID</td>
    </tr>
  </tbody>
</table>

<p>A decode script in Python is available at <code class="highlighter-rouge">util/decode_inst_dep_trace.py</code> that outputs the trace in ASCII format.</p>

<p><strong>Example of a trace in ASCII</strong></p>

<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>1,356521,COMP,8500::

2,35656,1,COMP,0:,1:

3,35660,1,LOAD,1748752,4,74,500:,2:

4,35660,1,COMP,0:,3:

5,35664,1,COMP,3000::,4

6,35666,1,STORE,1748752,4,74,1000:,3:,4,5

7,35666,1,COMP,3000::,4

8,35670,1,STORE,1748748,4,74,0:,6,3:,7

9,35670,1,COMP,500::,7
</code></pre></div></div>

<p>Each record in the instruction fetch trace has the following fields.</p>

<table>
  <thead>
    <tr>
      <th>Fields</th>
      <th>Discritption</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td>required uint64 tick  </td>
      <td>Timestamp of the access</td>
    </tr>
    <tr>
      <td>required uint32 cmd	 </td>
      <td>Read or Write (in this case always Read)</td>
    </tr>
    <tr>
      <td>required uint64 addr  </td>
      <td>Physical memory address</td>
    </tr>
    <tr>
      <td>required uint32 size  </td>
      <td>Size in bytes of data</td>
    </tr>
    <tr>
      <td>optional uint32 flags  </td>
      <td>Flags or attributes of the access</td>
    </tr>
    <tr>
      <td>optional uint64 pkt_id  </td>
      <td>Id of the access</td>
    </tr>
    <tr>
      <td>optional uint64 pc   </td>
      <td>Instruction address, i.e. the program counter</td>
    </tr>
  </tbody>
</table>

<p>The decode script in Python at <code class="highlighter-rouge">util/decode_packet_trace.py</code> can be used to output the trace in ASCII format.</p>

<p><strong>Compile dependencies</strong>:</p>

<p>You need to install google protocol buffer as the traces are recorded using this.</p>

<div class="language-sh highlighter-rouge"><div class="highlight"><pre class="highlight"><code>
<span class="nb">sudo </span>apt-get <span class="nb">install </span>protobuf-compiler
<span class="nb">sudo </span>apt-get <span class="nb">install </span>libprotobuf-dev

</code></pre></div></div>

<h3 id="scripts-and-options"><strong>Scripts and options</strong></h3>
<ul>
  <li>SE mode
    <ul>
      <li><code class="highlighter-rouge">build/ARM/gem5.opt [gem5.opt options] -d bzip_10Minsts configs/example/se.py [se.py options] --cpu-type=arm_detailed --caches --cmd=$M5_PATH/binaries/arm_arm/linux/bzip2 --options=$M5_PATH/data/bzip2/lgred/input/input.source -I 10000000 --elastic-trace-en --data-trace-file=deptrace.proto.gz --inst-trace-file=fetchtrace.proto.gz --mem-type=SimpleMemory</code></li>
    </ul>
  </li>
  <li>FS mode: Create a checkpoint for your region of interest and resume from the checkpoint but with O3 CPU model and tracing enabled
    <ul>
      <li><code class="highlighter-rouge">build/ARM/gem5.opt --outdir=m5out/bbench ./configs/example/fs.py [fs.py options] --benchmark bbench-ics</code></li>
      <li><code class="highlighter-rouge">build/ARM/gem5.opt --outdir=m5out/bbench/capture_10M ./configs/example/fs.py [fs.py options] --cpu-type=arm_detailed --caches --elastic-trace-en --data-trace-file=deptrace.proto.gz --inst-trace-file=fetchtrace.proto.gz --mem-type=SimpleMemory --checkpoint-dir=m5out/bbench -r 0 --benchmark bbench-ics -I 10000000</code></li>
    </ul>
  </li>
</ul>

<h2 id="replay-with-trace-cpu"><strong>Replay with Trace CPU</strong></h2>

<p>The execution trace generated above is then consumed by the Trace CPU as illustrated below.</p>

<p><img src="/assets/img/Trace_cpu_top_level.jpg" alt="Trace_cpu_top_level" /></p>

<p>The Trace CPU model inherits from the Base CPU and interfaces with data and instruction L1 caches. A diagram of the Trace CPU explaining the major logic and control blocks is shown below.</p>

<p><img src="/assets/img/Trace_cpu_detail.jpg" alt="Trace_CPU_details" /></p>

<h3 id="scripts-and-options-1"><strong>Scripts and options</strong></h3>

<ul>
  <li>A trace replay script in the examples folder can be used to play back SE and FS generated traces
    <ul>
      <li><code class="highlighter-rouge">build/ARM/gem5.opt [gem5.opt options] -d bzip_10Minsts_replay configs/example/etrace_replay.py [options] --cpu-type=trace --caches --data-trace-file=bzip_10Minsts/deptrace.proto.gz --inst-trace-file=bzip_10Minsts/fetchtrace.proto.gz --mem-size=4GB</code></li>
    </ul>
  </li>
</ul>

<table>
  <thead>
    <tr>
      <th>Fields</th>
      <th>Discritption</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td>required uint64 seq_num</td>
      <td>Timestamp of the access</td>
    </tr>
    <tr>
      <td>required RecordType type</td>
      <td>Read or Write (in this case always Read)</td>
    </tr>
    <tr>
      <td>optional uint64 p_addr</td>
      <td>Physical memory address if instruction is a load/store</td>
    </tr>
    <tr>
      <td>optional uint32 size</td>
      <td>Size in bytes of data if instruction is a load/store</td>
    </tr>
    <tr>
      <td>optional uint32 flags</td>
      <td>Flags or attributes of the access, ex. Uncacheable</td>
    </tr>
    <tr>
      <td>required uint64 rob_dep</td>
      <td>Past instruction number on which there is order (ROB) dependency</td>
    </tr>
    <tr>
      <td>required uint64 comp_delay</td>
      <td>Execution delay between the completion of the last dependency and the execution of the instruction</td>
    </tr>
    <tr>
      <td>repeated uint64 reg_dep</td>
      <td>Past instruction number on which there is RAW data dependency</td>
    </tr>
    <tr>
      <td>optional uint32 weight</td>
      <td>To account for committed instructions that were filtered out</td>
    </tr>
    <tr>
      <td>optional uint64 pc</td>
      <td>Instruction address, i.e. the program counter</td>
    </tr>
    <tr>
      <td>optional uint64 v_addr</td>
      <td>Virtual memory address if instruction is a load/store</td>
    </tr>
    <tr>
      <td>optional uint32 asid</td>
      <td>Address Space ID</td>
    </tr>
  </tbody>
</table>

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